1. Field of the Invention
This invention relates to memory controllers and, more particularly, to prefetch mechanisms for prefetching data from memory.
2. Description of the Related Art
Memory latency is frequently a factor in determining the performance (e.g. instructions executed per second) of a processor (and for that matter any device requiring access to system memory) in a given computer system. Over time, the operating frequencies of processors have increased dramatically, while the latency for access to dynamic random access memory (DRAM) in the typical computer system has not decreased as dramatically. Additionally, transmitting memory requests from the processor to the memory controller coupled to the memory system also requires time, which increases the memory latency. Accordingly, the number of clock cycles required to access the DRAM memory has increased, from latencies (as measured in clock cycles) of a few clock cycles, through tens of clock cycles, to over a hundred processor clocks in modern computer systems.
Processors have implemented caches to combat the effects of memory latency on processor performance. Caches are relatively small, low latency memories incorporated into the processor or coupled nearby. The caches store recently used instructions and/or data under the assumption that the recently used information may be accessed by the processor again. The caches may thus reduce the effective memory latency experienced by a processor by providing frequently accessed information more rapidly than if the information had to be retrieved from the memory system in response to each access.
Some processors have further improved memory latencies and memory bandwidth available to the processor by using an integrated a memory controller. Similarly, devices such as graphics controllers may have integrated memory controllers for accessing local graphics memory. In such processors and devices, one way that the memory bandwidth may be more effectively utilized is to predict the information that is to be accessed and to prefetch that information from the system memory and to store the prefetched information in a local memory cache or buffer. If the prediction is correct, the information may be a cache hit at the time of the actual request and thus the effective memory latency for actual requests may be decreased. Accordingly, an aggressive prefetch mechanism may be desirable.